1. Field of the Invention
The present invention relates to a power-up detection circuit for an integrated circuit and, more particularly, to a circuit for detecting a power supply input to the circuit and creating a pulse output signal each time that a circuit is energized by a source of power regardless of a varying rise time of the power supply voltage.
2. Description of the Prior An
When power is first applied to a variety of integrated circuits, it is often desirable to reset certain circuit elements such as logic flip-flops and memory shift registers to some predetermined initial state. Forcing the circuit elements to a predetermined state tends to prevent unpredictable and unwanted operations that sometimes occur during or shortly after the time interval required for the voltage at the power supply input terminal to rise to a steady-state value. This circuit initialization process is commonly achieved by a power-up detection circuit which detects the power supply to the circuit and supplies an initial pulse output signal to the various circuit elements for a brief period of time after the circuit is turned on.
As shown in FIG. 1, a conventional power-up detection circuit is commonly comprised of a P-channel metal-oxide semiconductor (P-MOS) transistor 1 having its gate connected to ground and its source connected to the power supply voltage Vdd, a P-MOS transistor 2 having its gate and drain commonly connected to a node N1 and its source connected to the drain of the P-MOS transistor 1, a P-MOS transistor 3 having its source-drain path connected between the power supply voltage Vdd and the node ND1 and its gate supplied with a feed-back signal from an inverter 7, an N-channel metal-oxide semiconductor (N-MOS) capacitor 4 having its gate connected to the node ND1 and its drain and source connected to ground, series inverters 5-7 which sequentially invert a signal outputted from the node ND1, a P-MOS capacitor 8 having its drain and source commonly connected to the power supply voltage Vdd and its gate connected to a drain-source connection point of the P-MOS transistors 1 and 2, a P-MOS capacitor 9 having its drain and source commonly connected to the power supply voltage Vdd and its gate connected to a node ND2 which is the output terminal of the inverter 5, and a pulse generating circuit 10 which generates a power-up detection pulse, corresponding to the output signal from the inverter 7.
When the power supply voltage Vdd is applied to the above described conventional circuit, the voltage is applied to node ND1 via turned-on P-MOS transistors 1 and 2, and the voltage of node ND1 is applied to inverter 5 with a predetermined delay time (R-C delay time) by P-MOS transistors 1, 2 and N-MOS capacitor 4. Therefore, the voltage at node ND1 is the power supply voltage with the predetermined delay time and thus the logic state of node ND1 transits from low to high after the delay time. The transition of the logic state at node ND1 is inverted by inverters 5-7, respectively.
By the way, when the logic state of node ND1 is low during the R-C delay time at the early stage of the operation, inverter 7 outputs a logic high signal to the gate of P-MOS transistor 3 to render it nonconductive. However, when the logic state of node ND1 becomes a logic high level after the R-C delay time, inverter 7 outputs a logic low level signal to the gate of P-MOS transistor 3, thus maintaining the logic state of node ND1 to be high with the conductive P-MOS transistor 3. As explained hereinabove, P-MOS transistor 3 maintains the logic state of node ND1 to be low during the R-C delay time, and maintains the logic state of node ND1 to be high after the R-C delay time. P-MOS capacitor 8 controls the amount of the current flow from P-MOS transistor 1 to P-MOS transistor 2. Also, P-MOS capacitor 9 supports the logic state of node ND2 to be high during the R-C delay time in which the logic state of node ND1 is low, which in turn causes the logic state of the output signal from inverter 7 to be low and thus renders P-MOS transistor 3 to be turned off. Pulse generating circuit 10 generates the power-up detection pulse by using the transition of the logic state from high to low of the signal outputted from inverter 7.
However, when the rise time of the power supply voltage Vdd varies such that a slow rising power supply voltage or a fast rising power supply voltage is applied to the conventional circuit, the delay time of the voltage at node ND1 has a wide range, causing an exact detection of the power supply input to be impossible. Furthermore, an exact detection of the power supply input is impossible in the conventional circuit, when the power supply voltage is applied again shortly after an abrupt interruption of the power supply.
The novel features which are believed to be characteristic of the present invention will be better understood from the following detailed description, considered in connection with the accompanying drawings, wherein various circuits employing the present invention are described.